How AND Gate found
AND GATE
To start with you have to understand transistors in a simple way. I will deal with CMOS since 99% of all logic that has ever existed (in number count) exists as CMOS.
There are two kinds of transistors used, PMOS and NMOS, here are their symbols:
Fig 1
The transistors are electrically controlled current sources/sinks. The PMOS will source current (the dotted line in the diagram shows current flow when on) from a power supply (attached to source) through the drain and into other circuits when the Gate voltage is LOWER than the source. The NMOS will sink current into ground through the drain into the source (which in this case you should think of as a sink).
Please note that I've taken some liberties with naming for the sake of clarity.
PMOS is usually connected to a positive voltage and NMOS is usually connected to negative voltages typically ground.
Interestingly you can stack the devices to make various functions. Stacking two PMOS gives a current source that is controlled by two voltages, stacking two NMOS gives a current sink that is controlled by two voltages.
Notice that both Voltage at A (we'll call it A) and B BOTH have to be below +V for current to flow. Also notice that Both C and D have to be higher than Ground (that funny hatched triangle symbol) for current to be sinked (sunk ?). You could say "Both A AND B have to low for current to flow" and "Both C AND D have to be high for current to flow".
Just like you can "stack" (actually put in series), you can parallel devices. enter image description here
You could say that "either A OR B can be low for current to flow" for the PMOS and you could say that "either C OR D can be high for current to flow" for the NMOS circuit.
You will notice that already we are using logic language to describe function (AND, OR) so now we can start piecing together circuits.
Electrical Engineering
How are logic gates created electronically?
Asked 11 years, 6 months ago
Modified 7 years, 5 months ago
Viewed 47k times
30
So we have AND, NOT, NAND, NOR, OR gates, but how are they created electronically/electrically?
For example, what makes NOT gate reverse the value?
transistorsdigital-logic
Share
Cite
Follow
edited Jan 7, 2013 at 0:52
placeholder's user avatar
placeholder
30.2k1010 gold badges6363 silver badges110110 bronze badges
asked Jan 6, 2013 at 17:29
user17534's user avatar
user17534
48122 gold badges55 silver badges55 bronze badges
4
Out of transistors. –
Dean
CommentedJan 6, 2013 at 17:34
Here is a blog post I wrote that shows how to physically make the circuits from transistors and explains why they work. I found it easiest to understand after practically making then rather than just reading theory. The circuits are based on diagrams from here. –
insano10
CommentedJun 25, 2016 at 17:13
Add a comment
5 Answers
Sorted by:
Highest score (default)
65
I've turned this into a community wiki so we can collect cool logic gate implementations to which to refer to in the future.
To start with you have to understand transistors in a simple way. I will deal with CMOS since 99% of all logic that has ever existed (in number count) exists as CMOS.
There are two kinds of transistors used, PMOS and NMOS, here are their symbols: Fig 1
The transistors are electrically controlled current sources/sinks. The PMOS will source current (the dotted line in the diagram shows current flow when on) from a power supply (attached to source) through the drain and into other circuits when the Gate voltage is LOWER than the source. The NMOS will sink current into ground through the drain into the source (which in this case you should think of as a sink).
Please note that I've taken some liberties with naming for the sake of clarity.
PMOS is usually connected to a positive voltage and NMOS is usually connected to negative voltages typically ground.
Interestingly you can stack the devices to make various functions. Stacking two PMOS gives a current source that is controlled by two voltages, stacking two NMOS gives a current sink that is controlled by two voltages.
enter image description here
Notice that both Voltage at A (we'll call it A) and B BOTH have to be below +V for current to flow. Also notice that Both C and D have to be higher than Ground (that funny hatched triangle symbol) for current to be sinked (sunk ?). You could say "Both A AND B have to low for current to flow" and "Both C AND D have to be high for current to flow".
Just like you can "stack" (actually put in series), you can parallel devices. enter image description here
You could say that "either A OR B can be low for current to flow" for the PMOS and you could say that "either C OR D can be high for current to flow" for the NMOS circuit.
You will notice that already we are using logic language to describe function (AND, OR) so now we can start piecing together circuits.
First off the Invertor:
When Vin is at ground, the PMOS is turned on and can source current, but the NMOS is off and cannot sink current. As a result, the Vout pin tries to put charge onto any available capacitance and charges that capacitance up until it reaches the V+ level.
Likewise when the Vin is High, the NMOS is turned on and can sink current, but the PMOS is now off and cannot source current. as a result, the Vout pin tries to pull charge off of any available capacitance and discharges that capacitance until it reaches the Ground level.
A "high" on the input gives a "low" on the output, a "low" on the input gives a "high" on the output. It inverts!
If you look at the symbol for both the PMOS and the NMOS you'see that the gate looks like a capacitor on the symbol. This is deliberate as a MOS transistor IS a capacitor and it is mainly this capacitance that is charged and discharged during operation. Current is the flow of charge per time and capacitance is the storage of charge per voltage. Transistors turn gate voltage into controlled currents that then charge and discharge gate capacitances that turns that change in charge back into a change in voltage.
Now for the first two input gate the NAND gate:
The NMOS "stack" will only ever sink current under one condition, and that is when BOTH A & B are high. Notice that for that condition that BOTH the PMOS are off (i.e. do not source current). So in that condition Vout will sink current and the Vout will be Low.
In all other conditions at least one of the PMOS will be sourcing current and the NMOS stack will not be able to sink current. The output is then charged up and Vout = high.
A B Out
0 0 1
0 1 1
1 0 1
1 1 0
This truth table shows that if Not(A&B) AKA NAND. 0 = gnd, 1 = V+.
To turn into a AND gate you just need to invert the output.
And it's truth table
A B Out
0 0 0
0 1 0
1 0 0
1 1 1
Comments
Post a Comment